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PRELIMINARY DATASHEET
This is similar in form to Eq. (3), where R OUT is used to
represent the characteristic impedance of the SAC?. However,
in this case a real R on the input side of the SAC is effectively
scaled by K 2 with respect to the output.
Assuming that R = 1 Ω , the effective R as seen from the secondary
side is 6.9 m Ω , with K = 1/12 .
A similar exercise should be performed with the additon of a
capacitor or shunt impedance at the input to the SAC.
A switch in series with V IN is added to the circuit. This is
depicted in Figure 15.
BCM 48 B x 040 y 200A00
Low impedance is a key requirement for powering a high-
current, low-voltage load efficiently. A switching regulation
stage should have minimal impedance while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit of scaling down series impedance
leading back to the source and scaling up shunt capacitance or
energy storage as a function of its K factor squared. However,
the benefits are not useful if the series impedance of the SAC
is too high. The impedance of the SAC must be low, i.e. well
beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables small magnetic
SAC
K = 1/32
IN
Vin
+
–
S
C
SAC?
K = 1/12
OUT
V Vout
components because magnetizing currents remain low. Small
magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
The two main terms of power loss in the BCM? module are:
- No load power dissipation (P NL ): defined as the power
used to power up the module with an enabled powertrain
at no load.
Figure 15 — Sine Amplitude Converter? with input capacitor
- Resistive loss (R OUT ): refers to the power loss across
the BCM module modeled as pure resistive impedance.
A change in V IN with the switch closed would result in a
change in capacitor current according to the following
equation:
P DISSIPATED = P NL + P ROUT
Therefore,
(10)
I C (t) = C
dV IN
dt
(7)
P OUT = P IN – P DISSIPATED = P IN – P NL – P ROUT
(11)
Assume that with the capacitor charged to V IN , the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
The above relations can be combined to calculate the overall
module efficiency:
I C = I OUT ? K
substituting Eq. (1) and (8) into Eq. (7) reveals:
C ? dV OUT
I OUT =
K 2 dt
(8)
(9)
η =
=
P OUT = P IN – P NL – P ROUT
P IN P IN
V IN ? I IN – P NL – (I OUT ) 2 ? R OUT
V IN ? I IN
(12)
( )
The equation in terms of the output has yielded a K 2 scaling
factor for C, specified in the denominator of the equation.
= 1–
P NL + (I OUT ) 2 ? R OUT
V IN ? I IN
A K factor less than unity results in an effectively larger
capacitance on the output when expressed in terms of the
input. With a K = 1/12 as shown in Figure 15,
C=1 μF would appear as C=144 μF when viewed
from the output.
Rev. 1.1
V?I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
7/2011
Page 12 of 18
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